1. Technical Field
A power-up signal generation circuit to be applied to various kinds of semiconductor devices is disclosed.
2. Description of the Related Art
FIG. 1 is a circuit diagram illustrating a conventional power-up signal generation circuit. The power-up signal generation circuit includes a plurality of PMOS transistors P11, P12, P13, and PCAP11, a plurality of NMOS transistors N11, NCAP1 and NCAP12 and a plurality of inverters INV11, INV12, INV13 and INV14.
The PMOS transistors P11 and P12 and the NMOS transistor N11 are coupled in series between a power supply voltage VDD and a ground voltage. The gate of the first PMOS transistor P11 is coupled to the drain thereof, and the gate of the second PMOS transistor P12 is coupled to the ground voltage. The gate of the first NMOS transistor N11 is coupled to the drain thereof, and the gate of the second NMOS transistor NCAP11, whose drain and source are coupled to each other and to the ground voltage, is coupled to the drain of the second PMOS transistor P12. The third PMOS transistor P13 is coupled between the power supply voltage VDD and a first node node11, that is connected to the drain of the second PMOS transistor P12. An input of the first inverter INV11 is coupled to the first node node11 and the output of the first inverter INV11 is coupled to the gate of the third PMOS transistor P13 and a second node node12. The drain and the source of the fourth PMOS transistor PCAP11, whose gate is coupled to the second node node12, are coupled to each other and to the power supply voltage VDD. An input of the second inverter INV12 is coupled to the second node node12. The drain and the source of the third NMOS transistor NCAP12, whose gate is coupled to a third node node13 that is connected to an output of the second inverter INV12, are coupled to each other and to the ground voltage. The third and fourth inverters INV13 and INV14 are coupled in series. An input of the third inverter INV13 is coupled to the third node node13. The fourth inverter INV14 receives an output signal from the third inverter INV13 and outputs a power-up signal PWRUP.
Hereinafter, an operation of the conventional power-up detection circuit will be described as follow:
If the power supply voltage VDD applied from an external circuit is increased, the voltage level of the first node node11 is increased from VSS to a predetermined voltage level according to a current ratio of the first PMOS transistor P11, the second PMOS transistor P12 and the first NMOS transistor N11. If the voltage level at the first node node11 is increased above a threshold voltage of the first inverter INV11, the voltage level at the second node node12 is initially increased as much as the increased power supply voltage VDD since the second node node12 is coupled to the gate of the fourth PMOS transistor PCAP11. The voltage level at the second node node12 is then reduced to the ground voltage VSS by the first inverter INV11. The power-up signal PWRUP1 is transitioned from a low level to a high level by passing through the inverters INV12, INV13 and INV14. Particularly, the external power supply voltage VDD applied to the circuit is detected and then the power-up signal PWRUP1, which represents that the operation voltage has been completely applied, is outputted.
The power supply voltage VDD is detected by using one or more capacitor elements NCAP or PCAP. According to the conventional power-up detecting circuit described above, if the external power supply voltage VDD is applied to the circuit and the applied external power voltage ramps up to its voltage level too slowly, there may be a problem that the power-up signal PWRUP1 is not appropriately generated since the detection operation of the capacitor element may fail during a slow voltage ramp-up. Recently, since there has been a tendency for the voltage level of the external power supply voltage VDD to be decreased, the above problem may be more serious.